전기전자기초실험 Arithmetic Circuit Design 결과보고서

- Objective : Understand the expression of negative binary number and 4-bit adder/subtracter with verilog simulation and FPGA Kit. Based on what we`ve learned before, make ALU(Arithmetic calculation. Then verify this with simulation and FPGA Kit)

- Procedure
1. 4-bit adder/subtracter
`SEL` clock is the a mark of arithmetic design. We assign the `SEL` to number `0`. As we pictured on the report, it is easily confirmed that pushing the `0` button means `-`. That`s why S=3 when A=0100, B=0001 in the picture of page 1 Waveform of 4-bit adder/subtracter. Followed picture means -8-2=-10 (with overflow). The overflow can be checked the 6th diode which turns on in the picture(Because it is out of range of expression). A assigns the `1234`, B assigns the `ABCD`. In the picture 0, 1, C pushed by operator. SO A = 1000, B = 0010, SEL=1.

As I mentioned before when out of arithmetic range happens, overflow will be 1. Followed table showed that as the example of 7+4=11 which has the overflow 1. The other case doesn`t have the overflow value. Add/Subtract mark depend on SEL.