Network-on-Chip(NoC) Topology

· 1. Jan Madsen, Shankar Mahadevan, Kashif Virk, Mercury Gonzalez
· 『Network-on-Chip Modeling for System level Multiprocessor Simulation』, IEEE, 2003
· 2. Giovanni De Micheli, Luca Benini
· 『Networks on Chips』, Morgan Kaufmann Publishers. 2006
· 3. Marcelo Erigson, Érika Cota, Marcelo Lubaszewski
· 『Test Scheduling in an Intra-Chip Network With Tree Topology』, South Symposium on Microelectronics
· 4. Davide Bertozzi and Luca Benini
· 『Xpipes : A Network-on-Chip Architecture for Gigascale Systems-on-Chip』,
· IEEE CIRCUITS AND SYSTEMS MAGAZINE, 2004
· 5. Jiri Jaros, Milos Ohlidal, Vaclav Dvorak
· 『Complexity of Collective Communications on NoCs』, IEEE, 2006
· 6. Luciano Bononi, Nicola Concer
· 『Simulation and Analysis of Network on Chip Architectures : Ring, Spidergon and 2D Mesh』, IEEE
· 7. Giuseppe Ascia, Vincenzo Catania, Maurizio Palesi
· 『Multi-objective Mapping for Mesh-based NoC Architectures』, IEEE
· 8. Luca Benini
· 『Application Specific NoC Design』, IEEE
· 9. Nilanjan Banerjee, Praveen Vellanki and Karam S. Chatha
· 『A Power and Performance Model for Network-on-Chip Architectures』, IEEE, 2004
· 10. Gerard Mas, Philippe Martin
· 『Network-on-Chip: the intelligence is in the wire』, IEEE, 2004
· 11. Krishnan Srinivasan, Karam S. Chatha
· 『ISIS : A Genetic Algorithm based Technique for Custom On-Chip
· Interconnection Network Synthesis』, IEEE, 2005
· 12. David A. Sigiienza-Tortosa, Jari Nurmi
· 『Topology Design for Global Link Optimization in Application Specific Network-on-Chips』, IEEE, 2004
· 13. L. Benini, D. Bertozzi
· 『Network-on-chip architectures and design methods』, IEE, 2005
· 14. Stefano Santi., Bill Lin, Ljupco Kocarev, Gian Mario Maggio, Riccardo Rovattiand Gianluca Setti
· 『On the Impact of Traffic Statistics on Quality of Service for
· Networks on Chip』, IEEE, 2005
· 15, Marcio Kreutz, Cesar Marcon, Luigi Carro, Ney Calazans and Altamiro A. Susin
· 『Energy and Latency Evaluation of NoC Topologies』, IEEE, 2005
· 16. Srhivasan Murali, Luca Benini, Giovanni De Micheli
· 『Mapping and Physical Planning of Networks-on-Chip rchitectures
· with Quality-of-Service Guarantees』, IEEE, 2005
· 17. Krishnan Srinivasan, Karam S. Chatha
· 『SAGA: Synthesis Technique for Guaranteed Throughput NoC Architectures』, IEEE, 2005
· 18. Cristian Grecu, Partha Pande, Baosheng Wang, Andre Ivanov, Res Saleh
· 『Methodologies and Algorithms for Testing Switch-Based NoC Interconnects』, IEEE, 2005
· 19. Krishnan Srinivasan, Karam S. Chatha
· 『A Methodology for Layout Aware Design and Optimization of Custom Network-on-Chip Architectures』, IEEE, 2006